The present invention relates to testing electronic devices, and more particularly to automating the testing of electronic devices at different operating speeds.
Many different characteristics of electronic devices are tested during and after their manufacturing process. One critical determination for many devices is identifying a maximum operating speed for which a device is rated. Due to manufacturing and processing variations of semiconductor devices, two similarly constructed devices often have different operating characteristics. One method of determining the rated operating speed of a device is to perform system-level tests at a clock speed and determine if either success or failure occurs. By system-level tests, it is meant that the device is tested in the environment and configuration in which it is to be ultimately used.
The current methods and systems for system-level testing CPU devices, or microprocessors, are time consuming and labor intensive, and therefore expensive as well. Typically, a device under test is manually inserted into a test station that operates at a specific fixed speed. At this station, a system level test is performed, automatically or under manual supervision, and after completion an operator manually separates CPU devices which pass from CPU devices which fail. The devices which pass are rated at the test station""s operating speed while the devices which fail are transported to a different test station with a lower operating speed. This cycle of testing, sorting and transporting is repeated until every CPU device is rated at some operating speed or outright rejected.
A similar arrangement, also known in the art, is to have a system test station which has a manually configurable speed setting. In this instance, the station""s operating speed is set, a plurality of CPU devices are tested, the operating speed is manually lowered, and then all failing devices are re-tested. This testing sequence is repeated until all CPU devices eventually pass at some operating speed or are ultimately rejected.
The prior art fails to provide an efficient and error-free method of performing system level tests. The manual nature of these previous methods for part placement, testing, and sorting leads to errors such as improperly inserted devices, incorrect error determinations, and inefficient device sorting.
This and other needs are met by embodiments of the present invention which provide system-level testing (SLT) of a CPU device that is performed in an automated test environment. Each device under test is automatically placed in the SLT station and a test is performed at an initial operating speed. A CPU device which passes the test is then automatically removed and placed in a storage container based on that operating speed, also known as a rating (or rated) speed. If the device fails the test, however, then it remains in the test station and the operating speed of the station is adjusted until the device is able to pass the test. Once successful, the device is automatically removed and placed in a storage container based on the operating speed at which it finally was successful. A device which is unable to pass a system-level test at any speed is automatically removed and placed in a reject bin. This testing procedure is repeated for a number of devices without requiring manual intervention to place the device in the SLT station, adjust the test operating speed, or binning the CPU device according to its rated speed.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.